BNL_EVENTS(3CPC) CPU Performance Counters Library Functions
NAME
bnl_events - processor model specific performance counter events
DESCRIPTION
This manual page describes events specific to the following Intel CPU
models and is derived from Intel's perfmon data. For more information,
please consult the Intel Software Developer's Manual or Intel's perfmon
website.
CPU models described by this document:
+o Family 0x6, Model 0x35 +o Family 0x6, Model 0x36 +o Family 0x6, Model 0x27 +o Family 0x6, Model 0x26 +o Family 0x6, Model 0x1c The following events are supported:
store_forwards.any All store forwards
store_forwards.good Good store forwards
reissue.any Micro-op reissues for any cause
reissue.any.ar Micro-op reissues for any cause (At Retirement)
misalign_mem_ref.split Memory references that cross an 8-byte boundary.
misalign_mem_ref.ld_split Load splits
misalign_mem_ref.st_split Store splits
misalign_mem_ref.split.ar Memory references that cross an 8-byte boundary (At Retirement)
misalign_mem_ref.ld_split.ar Load splits (At Retirement)
misalign_mem_ref.st_split.ar Store splits (Ar Retirement)
misalign_mem_ref.rmw_split ld-op-st splits
misalign_mem_ref.bubble Nonzero segbase 1 bubble
misalign_mem_ref.ld_bubble Nonzero segbase load 1 bubble
misalign_mem_ref.st_bubble Nonzero segbase store 1 bubble
misalign_mem_ref.rmw_bubble Nonzero segbase ld-op-st 1 bubble
segment_reg_loads.any Number of segment register loads.
prefetch.prefetcht0 Streaming SIMD Extensions (SSE) PrefetchT0 instructions
executed.
prefetch.prefetcht1 Streaming SIMD Extensions (SSE) PrefetchT1 instructions
executed.
prefetch.prefetcht2 Streaming SIMD Extensions (SSE) PrefetchT2 instructions
executed.
prefetch.sw_l2 Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2
instructions executed
prefetch.prefetchnta Streaming SIMD Extensions (SSE) Prefetch NTA instructions
executed
prefetch.hw_prefetch L1 hardware prefetch request
prefetch.software_prefetch Any Software prefetch
prefetch.software_prefetch.ar Any Software prefetch
data_tlb_misses.dtlb_miss Memory accesses that missed the DTLB.
data_tlb_misses.dtlb_miss_ld DTLB misses due to load operations.
data_tlb_misses.l0_dtlb_miss_ld L0 DTLB misses due to load operations.
data_tlb_misses.dtlb_miss_st DTLB misses due to store operations.
data_tlb_misses.l0_dtlb_miss_st L0 DTLB misses due to store operations
dispatch_blocked.any Memory cluster signals to block micro-op dispatch for any
reason
page_walks.walks Number of page-walks executed.
page_walks.cycles Duration of page-walks in core cycles
page_walks.d_side_walks Number of D-side only page walks
page_walks.d_side_cycles Duration of D-side only page walks
page_walks.i_side_walks Number of I-Side page walks
page_walks.i_side_cycles Duration of I-Side page walks
x87_comp_ops_exe.any.s Floating point computational micro-ops executed.
x87_comp_ops_exe.any.ar Floating point computational micro-ops retired.
x87_comp_ops_exe.fxch.s FXCH uops executed.
x87_comp_ops_exe.fxch.ar FXCH uops retired.
fp_assist.s Floating point assists.
fp_assist.ar Floating point assists for retired operations.
mul.s Multiply operations executed.
mul.ar Multiply operations retired
div.s Divide operations executed.
div.ar Divide operations retired
cycles_div_busy Cycles the divider is busy.
l2_ads.self Cycles L2 address bus is in use.
l2_dbus_busy.self Cycles the L2 cache data bus is busy.
l2_dbus_busy_rd.self Cycles the L2 transfers data to the core.
l2_lines_in.self.any L2 cache misses.
l2_lines_in.self.demand L2 cache misses.
l2_lines_in.self.prefetch L2 cache misses.
l2_m_lines_in.self L2 cache line modifications.
l2_lines_out.self.any L2 cache lines evicted.
l2_lines_out.self.demand L2 cache lines evicted.
l2_lines_out.self.prefetch L2 cache lines evicted.
l2_m_lines_out.self.any Modified lines evicted from the L2 cache
l2_m_lines_out.self.demand Modified lines evicted from the L2 cache
l2_m_lines_out.self.prefetch Modified lines evicted from the L2 cache
l2_ifetch.self.e_state L2 cacheable instruction fetch requests
l2_ifetch.self.i_state L2 cacheable instruction fetch requests
l2_ifetch.self.m_state L2 cacheable instruction fetch requests
l2_ifetch.self.s_state L2 cacheable instruction fetch requests
l2_ifetch.self.mesi L2 cacheable instruction fetch requests
l2_ld.self.any.e_state L2 cache reads
l2_ld.self.any.i_state L2 cache reads
l2_ld.self.any.m_state L2 cache reads
l2_ld.self.any.s_state L2 cache reads
l2_ld.self.any.mesi L2 cache reads
l2_ld.self.demand.e_state L2 cache reads
l2_ld.self.demand.i_state L2 cache reads
l2_ld.self.demand.m_state L2 cache reads
l2_ld.self.demand.s_state L2 cache reads
l2_ld.self.demand.mesi L2 cache reads
l2_ld.self.prefetch.e_state L2 cache reads
l2_ld.self.prefetch.i_state L2 cache reads
l2_ld.self.prefetch.m_state L2 cache reads
l2_ld.self.prefetch.s_state L2 cache reads
l2_ld.self.prefetch.mesi L2 cache reads
l2_st.self.e_state L2 store requests
l2_st.self.i_state L2 store requests
l2_st.self.m_state L2 store requests
l2_st.self.s_state L2 store requests
l2_st.self.mesi L2 store requests
l2_lock.self.e_state L2 locked accesses
l2_lock.self.i_state L2 locked accesses
l2_lock.self.m_state L2 locked accesses
l2_lock.self.s_state L2 locked accesses
l2_lock.self.mesi L2 locked accesses
l2_data_rqsts.self.e_state All data requests from the L1 data cache
l2_data_rqsts.self.i_state All data requests from the L1 data cache
l2_data_rqsts.self.m_state All data requests from the L1 data cache
l2_data_rqsts.self.s_state All data requests from the L1 data cache
l2_data_rqsts.self.mesi All data requests from the L1 data cache
l2_ld_ifetch.self.e_state All read requests from L1 instruction and data caches
l2_ld_ifetch.self.i_state All read requests from L1 instruction and data caches
l2_ld_ifetch.self.m_state All read requests from L1 instruction and data caches
l2_ld_ifetch.self.s_state All read requests from L1 instruction and data caches
l2_ld_ifetch.self.mesi All read requests from L1 instruction and data caches
l2_rqsts.self.any.e_state L2 cache requests
l2_rqsts.self.any.i_state L2 cache requests
l2_rqsts.self.any.m_state L2 cache requests
l2_rqsts.self.any.s_state L2 cache requests
l2_rqsts.self.any.mesi L2 cache requests
l2_rqsts.self.demand.e_state L2 cache requests
l2_rqsts.self.demand.m_state L2 cache requests
l2_rqsts.self.demand.s_state L2 cache requests
l2_rqsts.self.prefetch.e_state L2 cache requests
l2_rqsts.self.prefetch.i_state L2 cache requests
l2_rqsts.self.prefetch.m_state L2 cache requests
l2_rqsts.self.prefetch.s_state L2 cache requests
l2_rqsts.self.prefetch.mesi L2 cache requests
l2_rqsts.self.demand.i_state L2 cache demand requests from this core that missed the L2
l2_rqsts.self.demand.mesi L2 cache demand requests from this core
l2_reject_busq.self.any.e_state Rejected L2 cache requests
l2_reject_busq.self.any.i_state Rejected L2 cache requests
l2_reject_busq.self.any.m_state Rejected L2 cache requests
l2_reject_busq.self.any.s_state Rejected L2 cache requests
l2_reject_busq.self.any.mesi Rejected L2 cache requests
l2_reject_busq.self.demand.e_state Rejected L2 cache requests
l2_reject_busq.self.demand.i_state Rejected L2 cache requests
l2_reject_busq.self.demand.m_state Rejected L2 cache requests
l2_reject_busq.self.demand.s_state Rejected L2 cache requests
l2_reject_busq.self.demand.mesi Rejected L2 cache requests
l2_reject_busq.self.prefetch.e_state Rejected L2 cache requests
l2_reject_busq.self.prefetch.i_state Rejected L2 cache requests
l2_reject_busq.self.prefetch.m_state Rejected L2 cache requests
l2_reject_busq.self.prefetch.s_state Rejected L2 cache requests
l2_reject_busq.self.prefetch.mesi Rejected L2 cache requests
l2_no_req.self Cycles no L2 cache requests are pending
eist_trans Number of Enhanced Intel SpeedStep(R) Technology (EIST)
transitions
thermal_trip Number of thermal trips
cpu_clk_unhalted.core_p Core cycles when core is not halted
cpu_clk_unhalted.bus Bus cycles when core is not halted
l1d_cache.ld L1 Cacheable Data Reads
l1d_cache.st L1 Cacheable Data Writes
l1d_cache.all_ref L1 Data reads and writes
l1d_cache.all_cache_ref L1 Data Cacheable reads and writes
l1d_cache.repl L1 Data line replacements
l1d_cache.replm Modified cache lines allocated in the L1 data cache
l1d_cache.evict Modified cache lines evicted from the L1 data cache
bus_request_outstanding.all_agents Outstanding cacheable data read bus requests duration.
bus_request_outstanding.self Outstanding cacheable data read bus requests duration.
bus_bnr_drv.all_agents Number of Bus Not Ready signals asserted.
bus_bnr_drv.this_agent Number of Bus Not Ready signals asserted.
bus_drdy_clocks.all_agents Bus cycles when data is sent on the bus.
bus_drdy_clocks.this_agent Bus cycles when data is sent on the bus.
bus_lock_clocks.all_agents Bus cycles when a LOCK signal is asserted.
bus_lock_clocks.self Bus cycles when a LOCK signal is asserted.
bus_data_rcv.self Bus cycles while processor receives data.
bus_trans_brd.all_agents Burst read bus transactions.
bus_trans_brd.self Burst read bus transactions.
bus_trans_rfo.all_agents RFO bus transactions.
bus_trans_rfo.self RFO bus transactions.
bus_trans_wb.all_agents Explicit writeback bus transactions.
bus_trans_wb.self Explicit writeback bus transactions.
bus_trans_ifetch.all_agents Instruction-fetch bus transactions.
bus_trans_ifetch.self Instruction-fetch bus transactions.
bus_trans_inval.all_agents Invalidate bus transactions.
bus_trans_inval.self Invalidate bus transactions.
bus_trans_pwr.all_agents Partial write bus transaction.
bus_trans_pwr.self Partial write bus transaction.
bus_trans_p.all_agents Partial bus transactions.
bus_trans_p.self Partial bus transactions.
bus_trans_io.all_agents IO bus transactions.
bus_trans_io.self IO bus transactions.
bus_trans_def.all_agents Deferred bus transactions.
bus_trans_def.self Deferred bus transactions.
bus_trans_burst.all_agents Burst (full cache-line) bus transactions.
bus_trans_burst.self Burst (full cache-line) bus transactions.
bus_trans_mem.all_agents Memory bus transactions.
bus_trans_mem.self Memory bus transactions.
bus_trans_any.all_agents All bus transactions.
bus_trans_any.self All bus transactions.
ext_snoop.this_agent.any External snoops.
ext_snoop.this_agent.clean External snoops.
ext_snoop.this_agent.hit External snoops.
ext_snoop.this_agent.hitm External snoops.
ext_snoop.all_agents.any External snoops.
ext_snoop.all_agents.clean External snoops.
ext_snoop.all_agents.hit External snoops.
ext_snoop.all_agents.hitm External snoops.
bus_hit_drv.all_agents HIT signal asserted.
bus_hit_drv.this_agent HIT signal asserted.
bus_hitm_drv.all_agents HITM signal asserted.
bus_hitm_drv.this_agent HITM signal asserted.
busq_empty.self Bus queue is empty.
snoop_stall_drv.all_agents Bus stalled for snoops.
snoop_stall_drv.self Bus stalled for snoops.
bus_io_wait.self IO requests waiting in the bus queue.
icache.accesses Instruction fetches.
icache.hit Icache hit
icache.misses Icache miss
itlb.hit ITLB hits.
itlb.flush ITLB flushes.
itlb.misses ITLB misses.
cycles_icache_mem_stalled.icache_mem_stalled Cycles during which instruction fetches are stalled.
decode_stall.pfb_empty Decode stall due to PFB empty
decode_stall.iq_full Decode stall due to IQ full
br_inst_type_retired.cond All macro conditional branch instructions.
br_inst_type_retired.uncond All macro unconditional branch instructions, excluding calls
and indirects
br_inst_type_retired.ind All indirect branches that are not calls.
br_inst_type_retired.ret All indirect branches that have a return mnemonic
br_inst_type_retired.dir_call All non-indirect calls
br_inst_type_retired.ind_call All indirect calls, including both register and memory
indirect.
br_inst_type_retired.cond_taken Only taken macro conditional branch instructions
br_missp_type_retired.cond Mispredicted cond branch instructions retired
br_missp_type_retired.ind Mispredicted ind branches that are not calls
br_missp_type_retired.return Mispredicted return branches
br_missp_type_retired.ind_call Mispredicted indirect calls, including both register and memory
indirect.
br_missp_type_retired.cond_taken Mispredicted and taken cond branch instructions retired
macro_insts.non_cisc_decoded Non-CISC nacro instructions decoded
macro_insts.cisc_decoded CISC macro instructions decoded
macro_insts.all_decoded All Instructions decoded
simd_uops_exec.s SIMD micro-ops executed (excluding stores).
simd_uops_exec.ar SIMD micro-ops retired (excluding stores).
simd_sat_uop_exec.s SIMD saturated arithmetic micro-ops executed.
simd_sat_uop_exec.ar SIMD saturated arithmetic micro-ops retired.
simd_uop_type_exec.mul.s SIMD packed multiply micro-ops executed
simd_uop_type_exec.mul.ar SIMD packed multiply micro-ops retired
simd_uop_type_exec.shift.s SIMD packed shift micro-ops executed
simd_uop_type_exec.shift.ar SIMD packed shift micro-ops retired
simd_uop_type_exec.pack.s SIMD packed micro-ops executed
simd_uop_type_exec.pack.ar SIMD packed micro-ops retired
simd_uop_type_exec.unpack.s SIMD unpacked micro-ops executed
simd_uop_type_exec.unpack.ar SIMD unpacked micro-ops retired
simd_uop_type_exec.logical.s SIMD packed logical micro-ops executed
simd_uop_type_exec.logical.ar SIMD packed logical micro-ops retired
simd_uop_type_exec.arithmetic.s SIMD packed arithmetic micro-ops executed
simd_uop_type_exec.arithmetic.ar SIMD packed arithmetic micro-ops retired
inst_retired.any_p Instructions retired (precise event).
uops_retired.any Micro-ops retired.
uops_retired.stalled_cycles Cycles no micro-ops retired.
uops_retired.stalls Periods no micro-ops retired.
uops.ms_cycles This event counts the cycles where 1 or more uops are issued by
the micro-sequencer (MS), including microcode assists and
inserted flows, and written to the IQ.
machine_clears.smc Self-Modifying Code detected.
br_inst_retired.any Retired branch instructions.
br_inst_retired.pred_not_taken Retired branch instructions that were predicted not-taken.
br_inst_retired.mispred_not_taken Retired branch instructions that were mispredicted not-taken.
br_inst_retired.pred_taken Retired branch instructions that were predicted taken.
br_inst_retired.mispred_taken Retired branch instructions that were mispredicted taken.
br_inst_retired.taken Retired taken branch instructions.
br_inst_retired.any1 Retired branch instructions.
br_inst_retired.mispred Retired mispredicted branch instructions (precise event).
cycles_int_masked.cycles_int_masked Cycles during which interrupts are disabled.
cycles_int_masked.cycles_int_pending_and_masked Cycles during which interrupts are pending and disabled.
simd_inst_retired.packed_single Retired Streaming SIMD Extensions (SSE) packed-single
instructions.
simd_inst_retired.scalar_single Retired Streaming SIMD Extensions (SSE) scalar-single
instructions.
simd_inst_retired.scalar_double Retired Streaming SIMD Extensions 2 (SSE2) scalar-double
instructions.
simd_inst_retired.vector Retired Streaming SIMD Extensions 2 (SSE2) vector instructions.
hw_int_rcv Hardware interrupts received.
simd_comp_inst_retired.packed_single Retired computational Streaming SIMD Extensions (SSE) packed-
single instructions.
simd_comp_inst_retired.scalar_single Retired computational Streaming SIMD Extensions (SSE) scalar-
single instructions.
simd_comp_inst_retired.scalar_double Retired computational Streaming SIMD Extensions 2 (SSE2)
scalar-double instructions.
mem_load_retired.l2_hit Retired loads that hit the L2 cache (precise event).
mem_load_retired.l2_miss Retired loads that miss the L2 cache
mem_load_retired.dtlb_miss Retired loads that miss the DTLB (precise event).
simd_assist SIMD assists invoked.
simd_instr_retired SIMD Instructions retired.
simd_sat_instr_retired Saturated arithmetic instructions retired.
resource_stalls.div_busy Cycles issue is stalled due to div busy.
br_inst_decoded Branch instructions decoded
bogus_br Bogus branches
baclears.any BACLEARS asserted.
reissue.overlap_store Micro-op reissues on a store-load collision
reissue.overlap_store.ar Micro-op reissues on a store-load collision (At Retirement)
SEE ALSO
cpc(3CPC) https://download.01.org/perfmon/index/illumos June 18, 2018 illumos
