Tribblix: manual page: ivb

IVB_EVENTS(3CPC) CPU Performance Counters Library Functions

NAME

ivb_events - processor model specific performance counter events

DESCRIPTION

This manual page describes events specific to the following Intel CPU
models and is derived from Intel's perfmon data. For more information,
please consult the Intel Software Developer's Manual or Intel's perfmon
website.

CPU models described by this document:

+o Family 0x6, Model 0x3a

The following events are supported:

ld_blocks.store_forward
Loads blocked by overlapping with store buffer that cannot be
forwarded.

ld_blocks.no_sr
The number of times that split load operations are temporarily
blocked because all resources for handling the split accesses
are in use.

misalign_mem_ref.loads
Speculative cache-line split load uops dispatched to L1D.

misalign_mem_ref.stores
Speculative cache-line split Store-address uops dispatched to
L1D.

ld_blocks_partial.address_alias
False dependencies in MOB due to partial compare on address.

dtlb_load_misses.miss_causes_a_walk
Misses in all TLB levels that cause a page walk of any page
size from demand loads.

dtlb_load_misses.walk_completed
Misses in all TLB levels that caused page walk completed of any
size by demand loads.

dtlb_load_misses.walk_duration
Cycle PMH is busy with a walk due to demand loads.

dtlb_load_misses.large_page_walk_completed
Page walk for a large page completed for Demand load.

int_misc.recovery_cycles
Number of cycles waiting for the checkpoints in Resource
Allocation Table (RAT) to be recovered after Nuke due to all
other cases except JEClear (e.g. whenever a ucode assist is
needed like SSE exception, memory disambiguation, etc.)

int_misc.recovery_stalls_count
Number of occurences waiting for the checkpoints in Resource
Allocation Table (RAT) to be recovered after Nuke due to all
other cases except JEClear (e.g. whenever a ucode assist is
needed like SSE exception, memory disambiguation, etc.)

int_misc.recovery_cycles_any
Core cycles the allocator was stalled due to recovery from
earlier clear event for any thread running on the physical core
(e.g. misprediction or memory nuke).

uops_issued.any
Increments each cycle the # of Uops issued by the RAT to RS.
Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this
core.

uops_issued.stall_cycles
Cycles when Resource Allocation Table (RAT) does not issue Uops
to Reservation Station (RS) for the thread.

uops_issued.core_stall_cycles
Cycles when Resource Allocation Table (RAT) does not issue Uops
to Reservation Station (RS) for all threads.

uops_issued.flags_merge
Number of flags-merge uops allocated. Such uops adds delay.

uops_issued.slow_lea
Number of slow LEA or similar uops allocated. Such uop has 3
sources (e.g. 2 sources + immediate) regardless if as a result
of LEA instruction or not.

uops_issued.single_mul
Number of multiply packed/scalar single precision uops
allocated.

fp_comp_ops_exe.x87
Counts number of X87 uops executed.

fp_comp_ops_exe.sse_packed_double
Number of SSE* or AVX-128 FP Computational packed double-
precision uops issued this cycle.

fp_comp_ops_exe.sse_scalar_single
Number of SSE* or AVX-128 FP Computational scalar single-
precision uops issued this cycle.

fp_comp_ops_exe.sse_packed_single
Number of SSE* or AVX-128 FP Computational packed single-
precision uops issued this cycle.

fp_comp_ops_exe.sse_scalar_double
Counts number of SSE* or AVX-128 double precision FP scalar
uops executed.

simd_fp_256.packed_single
Counts 256-bit packed single-precision floating-point
instructions.

simd_fp_256.packed_double
Counts 256-bit packed double-precision floating-point
instructions.

arith.fpu_div_active
Cycles that the divider is active, includes INT and FP. Set
'edge =1, cmask=1' to count the number of divides.

arith.fpu_div
Divide operations executed.

l2_rqsts.demand_data_rd_hit
Demand Data Read requests that hit L2 cache.

l2_rqsts.all_demand_data_rd
Counts any demand and L1 HW prefetch data load requests to L2.

l2_rqsts.rfo_hit
RFO requests that hit L2 cache.

l2_rqsts.rfo_miss
Counts the number of store RFO requests that miss the L2 cache.

l2_rqsts.all_rfo
Counts all L2 store RFO requests.

l2_rqsts.code_rd_hit
Number of instruction fetches that hit the L2 cache.

l2_rqsts.code_rd_miss
Number of instruction fetches that missed the L2 cache.

l2_rqsts.all_code_rd
Counts all L2 code requests.

l2_rqsts.pf_hit
Counts all L2 HW prefetcher requests that hit L2.

l2_rqsts.pf_miss
Counts all L2 HW prefetcher requests that missed L2.

l2_rqsts.all_pf
Counts all L2 HW prefetcher requests.

l2_store_lock_rqsts.miss
RFOs that miss cache lines.

l2_store_lock_rqsts.hit_m
RFOs that hit cache lines in M state.

l2_store_lock_rqsts.all
RFOs that access cache lines in any state.

l2_l1d_wb_rqsts.miss
Not rejected writebacks that missed LLC.

l2_l1d_wb_rqsts.hit_e
Not rejected writebacks from L1D to L2 cache lines in E state.

l2_l1d_wb_rqsts.hit_m
Not rejected writebacks from L1D to L2 cache lines in M state.

l2_l1d_wb_rqsts.all
Not rejected writebacks from L1D to L2 cache lines in any
state.

longest_lat_cache.miss
This event counts each cache miss condition for references to
the last level cache.

longest_lat_cache.reference
This event counts requests originating from the core that
reference a cache line in the last level cache.

cpu_clk_unhalted.thread_p
Counts the number of thread cycles while the thread is not in a
halt state. The thread enters the halt state when it is running
the HLT instruction. The core frequency may change from time to
time due to power or thermal throttling.

cpu_clk_unhalted.thread_p_any
Core cycles when at least one thread on the physical core is
not in halt state.

cpu_clk_thread_unhalted.ref_xclk
Increments at the frequency of XCLK (100 MHz) when not halted.

cpu_clk_thread_unhalted.ref_xclk_any
Reference cycles when the at least one thread on the physical
core is unhalted. (counts at 100 MHz rate)

cpu_clk_unhalted.ref_xclk
Reference cycles when the thread is unhalted. (counts at 100
MHz rate)

cpu_clk_unhalted.ref_xclk_any
Reference cycles when the at least one thread on the physical
core is unhalted. (counts at 100 MHz rate)

cpu_clk_thread_unhalted.one_thread_active
Count XClk pulses when this thread is unhalted and the other is
halted.

cpu_clk_unhalted.one_thread_active
Count XClk pulses when this thread is unhalted and the other
thread is halted.

l1d_pend_miss.pending
Increments the number of outstanding L1D misses every cycle.
Set Cmask = 1 and Edge =1 to count occurrences.

l1d_pend_miss.pending_cycles
Cycles with L1D load Misses outstanding.

l1d_pend_miss.pending_cycles_any
Cycles with L1D load Misses outstanding from any thread on
physical core.

l1d_pend_miss.fb_full
Cycles a demand request was blocked due to Fill Buffers
inavailability.

dtlb_store_misses.miss_causes_a_walk
Miss in all TLB levels causes a page walk of any page size
(4K/2M/4M/1G).

dtlb_store_misses.walk_completed
Miss in all TLB levels causes a page walk that completes of any
page size (4K/2M/4M/1G).

dtlb_store_misses.walk_duration
Cycles PMH is busy with this walk.

dtlb_store_misses.stlb_hit
Store operations that miss the first TLB level but hit the
second and do not cause page walks.

load_hit_pre.sw_pf
Non-SW-prefetch load dispatches that hit fill buffer allocated
for S/W prefetch.

load_hit_pre.hw_pf
Non-SW-prefetch load dispatches that hit fill buffer allocated
for H/W prefetch.

ept.walk_cycles
Cycle count for an Extended Page table walk. The Extended Page
Directory cache is used by Virtual Machine operating systems
while the guest operating systems use the standard TLB caches.

l1d.replacement
Counts the number of lines brought into the L1 data cache.

move_elimination.int_eliminated
Number of integer Move Elimination candidate uops that were
eliminated.

move_elimination.simd_eliminated
Number of SIMD Move Elimination candidate uops that were
eliminated.

move_elimination.int_not_eliminated
Number of integer Move Elimination candidate uops that were not
eliminated.

move_elimination.simd_not_eliminated
Number of SIMD Move Elimination candidate uops that were not
eliminated.

cpl_cycles.ring0
Unhalted core cycles when the thread is in ring 0.

cpl_cycles.ring0_trans
Number of intervals between processor halts while thread is in
ring 0.

cpl_cycles.ring123
Unhalted core cycles when the thread is not in ring 0.

rs_events.empty_cycles
Cycles the RS is empty for the thread.

rs_events.empty_end
Counts end of periods where the Reservation Station (RS) was
empty. Could be useful to precisely locate Frontend Latency
Bound issues.

dtlb_load_misses.stlb_hit
Counts load operations that missed 1st level DTLB but hit the
2nd level.

offcore_requests_outstanding.demand_data_rd
Offcore outstanding Demand Data Read transactions in SQ to
uncore. Set Cmask=1 to count cycles.

offcore_requests_outstanding.cycles_with_demand_data_rd
Cycles when offcore outstanding Demand Data Read transactions
are present in SuperQueue (SQ), queue to uncore.

offcore_requests_outstanding.demand_data_rd_ge_6
Cycles with at least 6 offcore outstanding Demand Data Read
transactions in uncore queue.

offcore_requests_outstanding.demand_code_rd
Offcore outstanding Demand Code Read transactions in SQ to
uncore. Set Cmask=1 to count cycles.

offcore_requests_outstanding.cycles_with_demand_code_rd
Offcore outstanding code reads transactions in SuperQueue (SQ),
queue to uncore, every cycle.

offcore_requests_outstanding.demand_rfo
Offcore outstanding RFO store transactions in SQ to uncore. Set
Cmask=1 to count cycles.

offcore_requests_outstanding.cycles_with_demand_rfo
Offcore outstanding demand rfo reads transactions in SuperQueue
(SQ), queue to uncore, every cycle.

offcore_requests_outstanding.all_data_rd
Offcore outstanding cacheable data read transactions in SQ to
uncore. Set Cmask=1 to count cycles.

offcore_requests_outstanding.cycles_with_data_rd
Cycles when offcore outstanding cacheable Core Data Read
transactions are present in SuperQueue (SQ), queue to uncore.

lock_cycles.split_lock_uc_lock_duration
Cycles in which the L1D and L2 are locked, due to a UC lock or
split lock.

lock_cycles.cache_lock_duration
Cycles in which the L1D is locked.

idq.empty
Counts cycles the IDQ is empty.

idq.mite_uops
Increment each cycle # of uops delivered to IDQ from MITE path.
Set Cmask = 1 to count cycles.

idq.mite_cycles
Cycles when uops are being delivered to Instruction Decode
Queue (IDQ) from MITE path.

idq.dsb_uops
Increment each cycle. # of uops delivered to IDQ from DSB path.
Set Cmask = 1 to count cycles.

idq.dsb_cycles
Cycles when uops are being delivered to Instruction Decode
Queue (IDQ) from Decode Stream Buffer (DSB) path.

idq.ms_dsb_uops
Increment each cycle # of uops delivered to IDQ when MS_busy by
DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of
delivery.

idq.ms_dsb_cycles
Cycles when uops initiated by Decode Stream Buffer (DSB) are
being delivered to Instruction Decode Queue (IDQ) while
Microcode Sequenser (MS) is busy.

idq.ms_dsb_occur
Deliveries to Instruction Decode Queue (IDQ) initiated by
Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is
busy.

idq.all_dsb_cycles_4_uops
Counts cycles DSB is delivered four uops. Set Cmask = 4.

idq.all_dsb_cycles_any_uops
Counts cycles DSB is delivered at least one uops. Set Cmask =
1.

idq.ms_mite_uops
Increment each cycle # of uops delivered to IDQ when MS_busy by
MITE. Set Cmask = 1 to count cycles.

idq.all_mite_cycles_4_uops
Counts cycles MITE is delivered four uops. Set Cmask = 4.

idq.all_mite_cycles_any_uops
Counts cycles MITE is delivered at least one uops. Set Cmask =
1.

idq.ms_uops
Increment each cycle # of uops delivered to IDQ from MS by
either DSB or MITE. Set Cmask = 1 to count cycles.

idq.ms_cycles
Cycles when uops are being delivered to Instruction Decode
Queue (IDQ) while Microcode Sequenser (MS) is busy.

idq.ms_switches
Number of switches from DSB (Decode Stream Buffer) or MITE
(legacy decode pipeline) to the Microcode Sequencer.

idq.mite_all_uops
Number of uops delivered to IDQ from any path.

icache.hit
Number of Instruction Cache, Streaming Buffer and Victim Cache
Reads. both cacheable and noncacheable, including UC fetches.

icache.misses
Number of Instruction Cache, Streaming Buffer and Victim Cache
Misses. Includes UC accesses.

icache.ifetch_stall
Cycles where a code-fetch stalled due to L1 instruction-cache
miss or an iTLB miss.

itlb_misses.miss_causes_a_walk
Misses in all ITLB levels that cause page walks.

itlb_misses.walk_completed
Misses in all ITLB levels that cause completed page walks.

itlb_misses.walk_duration
Cycle PMH is busy with a walk.

itlb_misses.stlb_hit
Number of cache load STLB hits. No page walk.

itlb_misses.large_page_walk_completed
Completed page walks in ITLB due to STLB load misses for large
pages.

ild_stall.lcp
Stalls caused by changing prefix length of the instruction.

ild_stall.iq_full
Stall cycles due to IQ is full.

br_inst_exec.nontaken_conditional
Not taken macro-conditional branches.

br_inst_exec.taken_conditional
Taken speculative and retired macro-conditional branches.

br_inst_exec.taken_direct_jump
Taken speculative and retired macro-conditional branch
instructions excluding calls and indirects.

br_inst_exec.taken_indirect_jump_non_call_ret
Taken speculative and retired indirect branches excluding calls
and returns.

br_inst_exec.taken_indirect_near_return
Taken speculative and retired indirect branches with return
mnemonic.

br_inst_exec.taken_direct_near_call
Taken speculative and retired direct near calls.

br_inst_exec.taken_indirect_near_call
Taken speculative and retired indirect calls.

br_inst_exec.all_conditional
Speculative and retired macro-conditional branches.

br_inst_exec.all_direct_jmp
Speculative and retired macro-unconditional branches excluding
calls and indirects.

br_inst_exec.all_indirect_jump_non_call_ret
Speculative and retired indirect branches excluding calls and
returns.

br_inst_exec.all_indirect_near_return
Speculative and retired indirect return branches.

br_inst_exec.all_direct_near_call
Speculative and retired direct near calls.

br_inst_exec.all_branches
Counts all near executed branches (not necessarily retired).

br_misp_exec.nontaken_conditional
Not taken speculative and retired mispredicted macro
conditional branches.

br_misp_exec.taken_conditional
Taken speculative and retired mispredicted macro conditional
branches.

br_misp_exec.taken_indirect_jump_non_call_ret
Taken speculative and retired mispredicted indirect branches
excluding calls and returns.

br_misp_exec.taken_return_near
Taken speculative and retired mispredicted indirect branches
with return mnemonic.

br_misp_exec.taken_indirect_near_call
Taken speculative and retired mispredicted indirect calls.

br_misp_exec.all_conditional
Speculative and retired mispredicted macro conditional
branches.

br_misp_exec.all_indirect_jump_non_call_ret
Mispredicted indirect branches excluding calls and returns.

br_misp_exec.all_branches
Counts all near executed branches (not necessarily retired).

idq_uops_not_delivered.core
Count issue pipeline slots where no uop was delivered from the
front end to the back end when there is no back-end stall.

idq_uops_not_delivered.cycles_0_uops_deliv.core
Cycles per thread when 4 or more uops are not delivered to
Resource Allocation Table (RAT) when backend of the machine is
not stalled.

idq_uops_not_delivered.cycles_le_1_uop_deliv.core
Cycles per thread when 3 or more uops are not delivered to
Resource Allocation Table (RAT) when backend of the machine is
not stalled.

idq_uops_not_delivered.cycles_le_2_uop_deliv.core
Cycles with less than 2 uops delivered by the front end.

idq_uops_not_delivered.cycles_le_3_uop_deliv.core
Cycles with less than 3 uops delivered by the front end.

idq_uops_not_delivered.cycles_fe_was_ok
Counts cycles FE delivered 4 uops or Resource Allocation Table
(RAT) was stalling FE.

uops_dispatched_port.port_0
Cycles which a Uop is dispatched on port 0.

uops_dispatched_port.port_0_core
Cycles per core when uops are dispatched to port 0.

uops_dispatched_port.port_1
Cycles which a Uop is dispatched on port 1.

uops_dispatched_port.port_1_core
Cycles per core when uops are dispatched to port 1.

uops_dispatched_port.port_2
Cycles which a Uop is dispatched on port 2.

uops_dispatched_port.port_2_core
Uops dispatched to port 2, loads and stores per core
(speculative and retired).

uops_dispatched_port.port_3
Cycles which a Uop is dispatched on port 3.

uops_dispatched_port.port_3_core
Cycles per core when load or STA uops are dispatched to port 3.

uops_dispatched_port.port_4
Cycles which a Uop is dispatched on port 4.

uops_dispatched_port.port_4_core
Cycles per core when uops are dispatched to port 4.

uops_dispatched_port.port_5
Cycles which a Uop is dispatched on port 5.

uops_dispatched_port.port_5_core
Cycles per core when uops are dispatched to port 5.

resource_stalls.any
Cycles Allocation is stalled due to Resource Related reason.

resource_stalls.rs
Cycles stalled due to no eligible RS entry available.

resource_stalls.sb
Cycles stalled due to no store buffers available (not including
draining form sync).

resource_stalls.rob
Cycles stalled due to re-order buffer full.

cycle_activity.cycles_l2_pending
Cycles with pending L2 miss loads. Set AnyThread to count per
core.

cycle_activity.cycles_l2_miss
Cycles while L2 cache miss load* is outstanding.

cycle_activity.cycles_ldm_pending
Cycles with pending memory loads. Set AnyThread to count per
core.

cycle_activity.cycles_mem_any
Cycles while memory subsystem has an outstanding load.

cycle_activity.cycles_no_execute
Total execution stalls.

cycle_activity.stalls_total
Total execution stalls.

cycle_activity.stalls_l2_pending
Number of loads missed L2.

cycle_activity.stalls_l2_miss
Execution stalls while L2 cache miss load* is outstanding.

cycle_activity.stalls_ldm_pending
Execution stalls due to memory subsystem.

cycle_activity.stalls_mem_any
Execution stalls while memory subsystem has an outstanding
load.

cycle_activity.cycles_l1d_pending
Cycles with pending L1 cache miss loads. Set AnyThread to count
per core.

cycle_activity.cycles_l1d_miss
Cycles while L1 cache miss demand load is outstanding.

cycle_activity.stalls_l1d_pending
Execution stalls due to L1 data cache miss loads. Set
Cmask=0CH.

cycle_activity.stalls_l1d_miss
Execution stalls while L1 cache miss demand load is
outstanding.

lsd.uops
Number of Uops delivered by the LSD.

lsd.cycles_active
Cycles Uops delivered by the LSD, but didn't come from the
decoder.

dsb2mite_switches.count
Number of DSB to MITE switches.

dsb2mite_switches.penalty_cycles
Cycles DSB to MITE switches caused delay.

dsb_fill.exceed_dsb_lines
DSB Fill encountered > 3 DSB lines.

itlb.itlb_flush
Counts the number of ITLB flushes, includes 4k/2M/4M pages.

offcore_requests.demand_data_rd
Demand data read requests sent to uncore.

offcore_requests.demand_code_rd
Demand code read requests sent to uncore.

offcore_requests.demand_rfo
Demand RFO read requests sent to uncore, including regular
RFOs, locks, ItoM.

offcore_requests.all_data_rd
Data read requests sent to uncore (demand and prefetch).

uops_executed.thread
Counts total number of uops to be executed per-thread each
cycle. Set Cmask = 1, INV =1 to count stall cycles.

uops_executed.stall_cycles
Counts number of cycles no uops were dispatched to be executed
on this thread.

uops_executed.cycles_ge_1_uop_exec
Cycles where at least 1 uop was executed per-thread.

uops_executed.cycles_ge_2_uops_exec
Cycles where at least 2 uops were executed per-thread.

uops_executed.cycles_ge_3_uops_exec
Cycles where at least 3 uops were executed per-thread.

uops_executed.cycles_ge_4_uops_exec
Cycles where at least 4 uops were executed per-thread.

uops_executed.core
Counts total number of uops to be executed per-core each cycle.

uops_executed.core_cycles_ge_1
Cycles at least 1 micro-op is executed from any thread on
physical core.

uops_executed.core_cycles_ge_2
Cycles at least 2 micro-op is executed from any thread on
physical core.

uops_executed.core_cycles_ge_3
Cycles at least 3 micro-op is executed from any thread on
physical core.

uops_executed.core_cycles_ge_4
Cycles at least 4 micro-op is executed from any thread on
physical core.

uops_executed.core_cycles_none
Cycles with no micro-ops executed from any thread on physical
core.

offcore_requests_buffer.sq_full
Cases when offcore requests buffer cannot take more entries for
core.

tlb_flush.dtlb_thread
DTLB flush attempts of the thread-specific entries.

tlb_flush.stlb_any
Count number of STLB flush attempts.

page_walks.llc_miss
Number of any page walk that had a miss in LLC.

inst_retired.any_p
Number of instructions at retirement.

inst_retired.prec_dist
Precise instruction retired event with HW to reduce effect of
PEBS shadow in IP distribution.

other_assists.avx_store
Number of assists associated with 256-bit AVX store operations.

other_assists.avx_to_sse
Number of transitions from AVX-256 to legacy SSE when penalty
applicable.

other_assists.sse_to_avx
Number of transitions from SSE to AVX-256 when penalty
applicable.

other_assists.any_wb_assist
Number of times any microcode assist is invoked by HW upon uop
writeback.

uops_retired.all
Retired uops.

uops_retired.stall_cycles
Cycles without actually retired uops.

uops_retired.total_cycles
Cycles with less than 10 actually retired uops.

uops_retired.core_stall_cycles
Cycles without actually retired uops.

uops_retired.retire_slots
Retirement slots used.

machine_clears.count
Number of machine clears (nukes) of any type.

machine_clears.memory_ordering
Counts the number of machine clears due to memory order
conflicts.

machine_clears.smc
Number of self-modifying-code machine clears detected.

machine_clears.maskmov
Counts the number of executed AVX masked load operations that
refer to an illegal address range with the mask bits set to 0.

br_inst_retired.all_branches
Branch instructions at retirement.

br_inst_retired.conditional
Conditional branch instructions retired.

br_inst_retired.near_call
Direct and indirect near call instructions retired.

br_inst_retired.near_call_r3
Direct and indirect macro near call instructions retired
(captured in ring 3).

br_inst_retired.all_branches_pebs
All (macro) branch instructions retired.

br_inst_retired.near_return
Return instructions retired.

br_inst_retired.not_taken
Counts the number of not taken branch instructions retired.

br_inst_retired.near_taken
Taken branch instructions retired.

br_inst_retired.far_branch
Number of far branches retired.

br_misp_retired.all_branches
Mispredicted branch instructions at retirement.

br_misp_retired.conditional
Mispredicted conditional branch instructions retired.

br_misp_retired.all_branches_pebs
Mispredicted macro branch instructions retired.

br_misp_retired.near_taken
number of near branch instructions retired that were
mispredicted and taken.

fp_assist.x87_output
Number of X87 FP assists due to output values.

fp_assist.x87_input
Number of X87 FP assists due to input values.

fp_assist.simd_output
Number of SIMD FP assists due to output values.

fp_assist.simd_input
Number of SIMD FP assists due to input values.

fp_assist.any
Cycles with any input/output SSE* or FP assists.

rob_misc_events.lbr_inserts
Count cases of saving new LBR records by hardware.

mem_uops_retired.stlb_miss_loads
Retired load uops that miss the STLB. (Precise Event)

mem_uops_retired.stlb_miss_stores
Retired store uops that miss the STLB. (Precise Event)

mem_uops_retired.lock_loads
Retired load uops with locked access. (Precise Event)

mem_uops_retired.split_loads
Retired load uops that split across a cacheline boundary.
(Precise Event)

mem_uops_retired.split_stores
Retired store uops that split across a cacheline boundary.
(Precise Event)

mem_uops_retired.all_loads
All retired load uops. (Precise Event)

mem_uops_retired.all_stores
All retired store uops. (Precise Event)

mem_load_uops_retired.l1_hit
Retired load uops with L1 cache hits as data sources.

mem_load_uops_retired.l2_hit
Retired load uops with L2 cache hits as data sources.

mem_load_uops_retired.llc_hit
Retired load uops which data sources were data hits in LLC
without snoops required.

mem_load_uops_retired.l1_miss
Retired load uops which data sources following L1 data-cache
miss.

mem_load_uops_retired.l2_miss
Retired load uops with L2 cache misses as data sources.

mem_load_uops_retired.llc_miss
Miss in last-level (L3) cache. Excludes Unknown data-source.

mem_load_uops_retired.hit_lfb
Retired load uops which data sources were load uops missed L1
but hit FB due to preceding miss to the same cache line with
data not ready.

mem_load_uops_llc_hit_retired.xsnp_miss
Retired load uops which data sources were LLC hit and cross-
core snoop missed in on-pkg core cache.

mem_load_uops_llc_hit_retired.xsnp_hit
Retired load uops which data sources were LLC and cross-core
snoop hits in on-pkg core cache.

mem_load_uops_llc_hit_retired.xsnp_hitm
Retired load uops which data sources were HitM responses from
shared LLC.

mem_load_uops_llc_hit_retired.xsnp_none
Retired load uops which data sources were hits in LLC without
snoops required.

mem_load_uops_llc_miss_retired.local_dram
Retired load uops whose data source was local memory (cross-
socket snoop not needed or missed).

baclears.any
Number of front end re-steers due to BPU misprediction.

l2_trans.demand_data_rd
Demand Data Read requests that access L2 cache.

l2_trans.rfo
RFO requests that access L2 cache.

l2_trans.code_rd
L2 cache accesses when fetching instructions.

l2_trans.all_pf
Any MLC or LLC HW prefetch accessing L2, including rejects.

l2_trans.l1d_wb
L1D writebacks that access L2 cache.

l2_trans.l2_fill
L2 fill requests that access L2 cache.

l2_trans.l2_wb
L2 writebacks that access L2 cache.

l2_trans.all_requests
Transactions accessing L2 pipe.

l2_lines_in.i
L2 cache lines in I state filling L2.

l2_lines_in.s
L2 cache lines in S state filling L2.

l2_lines_in.e
L2 cache lines in E state filling L2.

l2_lines_in.all
L2 cache lines filling L2.

l2_lines_out.demand_clean
Clean L2 cache lines evicted by demand.

l2_lines_out.demand_dirty
Dirty L2 cache lines evicted by demand.

l2_lines_out.pf_clean
Clean L2 cache lines evicted by the MLC prefetcher.

l2_lines_out.pf_dirty
Dirty L2 cache lines evicted by the MLC prefetcher.

l2_lines_out.dirty_all
Dirty L2 cache lines filling the L2.

sq_misc.split_lock
tbd

NAME

DESCRIPTION

SEE ALSO