Tribblix: manual page: snr

SNR_EVENTS(3CPC) CPU Performance Counters Library Functions

NAME

snr_events - processor model specific performance counter events

DESCRIPTION

This manual page describes events specific to the following Intel CPU
models and is derived from Intel's perfmon data. For more information,
please consult the Intel Software Developer's Manual or Intel's perfmon
website.

CPU models described by this document:

+o Family 0x6, Model 0x86

The following events are supported:

dtlb_load_misses.walk_completed_4k
Counts the number of page walks completed due to demand data
loads (including SW prefetches) whose address translations
missed in all TLB levels and were mapped to 4K pages. The page
walks can end with or without a page fault.

dtlb_load_misses.walk_completed_2m_4m
Counts the number of completed page walks due to a demand load
(including SW prefetches) whose address translations missed in
all TLB levels and were mapped to 2M or 4M pages. The page
walks can end with or without a page fault.

longest_lat_cache.miss
Counts the number of memory requests that miss in the last
level cache. If the platform has an L3 cache, last level cache
is the L3, otherwise it is the L2 cache. Counts on a per core
basis.

longest_lat_cache.reference
Counts cacheable memory requests that access the Last Level
Cache. Requests include Demand Loads, Reads for
Ownership(RFO), Instruction fetches and L1 HW prefetches. If
the platform has an L3 cache, last level cache is the L3,
otherwise it is the L2.

cpu_clk_unhalted.core_p
Counts the number of core cycles while the core is not in a
halt state. The core enters the halt state when it is running
the HLT instruction. The core frequency may change from time to
time. For this reason this event may have a changing ratio with
regards to time. This event uses a programmable general
purpose performance counter.

cpu_clk_unhalted.ref
Counts reference cycles (at TSC frequency) when core is not
halted. This event uses a programmable general purpose perfmon
counter.

dtlb_store_misses.walk_completed_4k
Counts page walks completed due to demand data stores whose
address translations missed in the TLB and were mapped to 4K
pages. The page walks can end with or without a page fault.

dtlb_store_misses.walk_completed_2m_4m
Counts the number of page walks completed due to demand data
stores whose address translations missed in the TLB and were
mapped to 2M or 4M pages. The page walks can end with or
without a page fault.

topdown_fe_bound.all
tbd

topdown_bad_speculation.all
Counts the number of issue slots that were not consumed by the
backend because allocation is stalled due to a mispredicted
jump or a machine clear. Counts all issue slots blocked during
this recovery window including relevant microcode flows and
while uops are not yet available in the IQ. Also, includes the
issue slots that were consumed by the backend but were thrown
away because they were younger than the mispredict or machine
clear.

topdown_be_bound.all
tbd

icache.misses
Counts requests to the Instruction Cache (ICache) for one or
more bytes in an ICache Line and that cache line is not in the
ICache (miss). The event strives to count on a cache line
basis, so that multiple accesses which miss in a single cache
line count as one ICACHE.MISS. Specifically, the event counts
when straight line code crosses the cache line boundary, or
when a branch target is to a new line, and that cache line is
not in the ICache.

icache.accesses
Counts requests to the Instruction Cache (ICache) for one or
more bytes in an ICache Line. The event strives to count on a
cache line basis, so that multiple fetches to a single cache
line count as one ICACHE.ACCESS. Specifically, the event
counts when accesses from straight line code crosses the cache
line boundary, or when a branch target is to a new line.

itlb.fills
Counts the number of times the machine was unable to find a
translation in the Instruction Translation Lookaside Buffer
(ITLB) and new translation was filled into the ITLB. The event
is speculative in nature, but will not count translations (page
walks) that are begun and not finished, or translations that
are finished but not filled into the ITLB.

itlb_misses.walk_completed_4k
Counts page walks completed due to instruction fetches whose
address translations missed in the TLB and were mapped to 4K
pages. The page walks can end with or without a page fault.

itlb_misses.walk_completed_2m_4m
Counts page walks completed due to instruction fetches whose
address translations missed in the TLB and were mapped to 2M or
4M pages. The page walks can end with or without a page fault.

inst_retired.any_p
Counts the number of instructions that retire execution. For
instructions that consist of multiple uops, this event counts
the retirement of the last uop of the instruction. The event
continues counting during hardware interrupts, traps, and
inside interrupt handlers. This is an architectural
performance event. This event uses a Programmable general
purpose perfmon counter. *This event is Precise Event capable:
The EventingRIP field in the PEBS record is precise to the
address of the instruction which caused the event.

topdown_retiring.all
Count the number of uops retired

machine_clears.any
Counts all machine clears due to, but not limited to memory
ordering, memory disambiguation, SMC, page faults and FP
assist.

br_inst_retired.all_branches
Counts branch instructions retired for all branch types. This
event is Precise Event capable. This is an architectural event.

br_misp_retired.all_branches
Counts the number of mispredicted branch instructions retired
for all branch types. This event is Precise Event capable. This
is an architectural event.

cycles_div_busy.any
Counts cycles the floating point divider or integer divider or
both are busy. Does not imply a stall waiting for either
divider.

mem_uops_retired.all_loads
Counts the number of load uops retired. This event is Precise
Event capable

mem_uops_retired.all_stores
Counts the number of store uops retired. This event is Precise
Event capable

mem_load_uops_retired.l1_hit
Counts the number of load uops retired that hit the level 1
data cache

mem_load_uops_retired.l2_hit
Counts the number of load uops retired that hit in the level 2
cache

mem_load_uops_retired.l3_hit
Counts the number of load uops retired that miss in the level 3
cache

mem_load_uops_retired.l1_miss
Counts the number of load uops retired that miss in the level 1
data cache

mem_load_uops_retired.l2_miss
Counts the number of load uops retired that miss in the level 2
cache

NAME

DESCRIPTION

SEE ALSO